Simulation FabricationFiber to chip coupling
Fabrication
SEM of a CGR device fabricated in Si

CGR devices are fabricated on SOI substrates consisting of a 2-ım-thick buried oxide layer and a 340-nm-thick device layer. The devices have been defined by electron-beam lithography (EBL) using Hydrogen Silsesquioxane (HSQ) as negative tone resist. Then pattern transfer has been achieved in a HBr-chemistry-based inductively coupled reactive-ion etch process using a two-step process. Pure HBr is used in the main etch step. The etching time for this step is set to stop at a residual top-Si thickness of 20 nm. Then the etch condition were changed to the second or overetch step. For this part a mixture of HBr and O2 is used. The overetch step exhibits an excellent selectivity between the top-Si and the buried oxide. The entire process flow, including both lithography and etching, is optimized to minimize the surface roughness of the CGRs. A scanning electron microscope (SEM) of a CGR device is shown in Fig. 3.

More Information: